Technical Field
This invention relates generally to the field of semiconductors, and more particularly, to forming a nitride spacer to protect a finFET device.
Related Art
A typical integrated circuit (IC) chip includes a stack of several levels or sequentially formed layers of shapes. Each layer is stacked or overlaid on a prior layer and patterned to form the shapes that define devices (e.g., field effect transistors (FETs)) and connect the devices into circuits. In a typical state of the art complementary insulated gate FET process, such as what is normally referred to as CMOS, layers are formed on a wafer to form the devices on a surface of the wafer. Further, the surface may be the surface of a silicon layer on a silicon on insulator (SOI) wafer. A simple FET is formed by the intersection of two shapes, a gate layer rectangle on a silicon island formed from the silicon surface layer. Each of these layers of shapes, also known as mask levels or layers, may be created or printed optically through well known photolithographic masking, developing and level definition, e.g., etching, implanting, deposition, etc.
The FinFET is a transistor design that attempts to overcome the issues of short-channel effect encountered by deep submicron transistors, such as drain-induced barrier lowering (DIBL). Such effects make it harder for the voltage on a gate electrode to deplete the channel underneath and stop the flow of carriers through the channel—in other words, to turn the transistor off. By raising the channel above the surface of the wafer instead of creating the channel just below the surface, it is possible to wrap the gate around all but one of its sides, providing much greater electrostatic control over the carriers within it.
In FinFET technology, preservation of the cap oxide on top of the gate, gate oxide around the fins, and the fin profiles is critical for the development of device yield. However, with current approaches, the oxide on top of the gates, gate oxide, as well as the fins, are eroded after the post-PC block implant layering. For example, as shown in the prior art device 100 of FIGS. 1(a)-1(b), oxide 102 on top of each gate 104 is left open post lithography and development, which exposes oxide 102 and fins 106 to all processing steps that follow (e.g., descum, implants, resist strips, etc.).
Furthermore, in areas of device 100 where there are no gates covering fins 106, there is vulnerability to gate oxide 102 and fins 106 themselves. That is, following the implants, photoresist 108 will be stripped using certain clean and ashing processes. These can affect the implanted oxide as well as amorphized fins 106. The y-cut area that includes the gates experiences some oxide loss on top of gates 104 in the areas that were uncovered by resist 108. The properties of oxide 102 on top of each gate 104 are changed post implantation, therefore weakening oxide 102. As a result, when resist 108 is stripped away, oxide 102 in the open area is stripped from the top of each gate 104. This is problematic because oxide 102 protects the nitride hardmask during subsequent formation of the source/drain (S/D) epitaxial layers. If there is no oxide remaining at the time of S/D epitaxial layer processing, the reactive ion etch (RIE) processes used will destroy this hardmask, causing a misprocess. In the x-cut area that has open fin area (e.g., shown in FIG. 2(b)), the fins become amorphized post implantation, weakening the silicon so that the cleans processes are able to erode the tops of fins 206, as shown in FIG. 2(a). Fin erosion is problematic because the fins in finFET technology are the channels. If the channels are damaged, all electrical parameters are negatively affected.